1. Field of the Invention.
The present invention relates to data processing systems and, in particular, to an interrupt-acknowledgement circuit that generates a single interrupt signal when a plurality of events are detected and that allows a host device to process all of the detected events without delayed processing, spurious interrupts, or additional overhead.
2. Description of the Related Art.
When a peripheral device regularly detects events which are processed by a host device, a simple interrupt-acknowledgement protocol can be utilized to define the communications between the peripheral device and the host device. Under a simple interrupt-acknowledgement protocol, the peripheral device typically detects a single event, generates a single interrupt signal in response to the detected event, and then ignores subsequent events until the interrupt signal is acknowledged by the host device (i.e., the host device modifies a register on the peripheral device).
Upon receiving the interrupt signal, the host device typically processes the event and then acknowledges the interrupt signal, thereby enabling the peripheral device to detect the next event. FIG. 1 shows a timing diagram which illustrates the operation of the host device and the peripheral device under a simple interrupt-acknowledgement protocol.
The detection of a series of events by the peripheral device is represented in FIG. 1 by a series of event pulses 10 where the falling edge 12 of each event pulse 10 represents the detection of a complete event. As shown in FIG. 1, the peripheral device generates the rising edge 14 of an interrupt signal V.sub.I in response to the falling edge 12 of a detected event.
The processing of each event 10 by the host device is represented in FIG. 1 by a series of processing pulses 16. As further shown in FIG. 1, the host device begins processing each event 10 a leading delay time T1 after the rising edge 14 of the interrupt signal V.sub.I is generated. The host device completes the processing of the event 10 and then generates an acknowledgement signal V.sub.A which is received by the peripheral device a trailing delay time T2 after the event has been processed, thereby causing the interrupt signal V.sub.I to be deasserted. The leading and trailing delay times T1 and T2 can represent, for example, the time required to communicate with the peripheral device via a bus.
While the relationship between the event, the interrupting signal, and the acknowledgement signal are well defined and robust, the simple interrupt-acknowledgement protocol is not very practical in environments where the events are received in bursts instead of being regularly spaced as shown in FIG. 1.
When events are received in bursts, as is the case with the network interface device of a local area network, a peripheral device which, as stated above, ignores intervening events can potentially lose all of the data packets transmitted while the interrupt signal is asserted.
To avoid a potential loss of data, most modern network interface devices utilize a many-to-one mapping protocol which allows the network interface device to receive multiple packets from the network. Under a process-then-acknowledge many-to-one protocol, the peripheral device typically detects a burst of packets and then generates a single interrupt signal in response to the first packet detected.
Upon receiving the interrupt signal, the host device typically processes all of the packets detected by the network interface device and then acknowledges the interrupt signal. FIG. 2 shows a timing diagram which illustrates the operation of the host device and the network interface device under a process-then-acknowledge many-to-one protocol.
The detection of a burst of packets by the network interface device is represented in FIG. 2 as a series of packet pulses 20 where the falling edge 22 represents the detection of a first complete packet. As with the peripheral device, the network interface device generates the rising edge 24 of an interrupt signal V.sub.II in response to the falling edge 22 of the first detected packet.
The processing of each packet 20 by the host device is represented in FIG. 2 by a series of packet processing pulses 26. As shown in FIG. 2, the host device processes all of the packets 20 detected by the network interface device and then acknowledges the interrupt signal V.sub.II the trailing delay time T2 after the last packet is processed.
The principal disadvantage of the process-then-acknowledge many-to-one protocol as described above is the occurrence of a delayed notification condition between the host device and the network interface device. A delayed notification condition occurs when the host device completes the processing of all the packets detected by the network interface device at approximately the same time that the network interface device detects a new packet.
FIG. 3 shows a timing diagram which illustrates a delayed notification from the network interface device to the host device under a process-then-acknowledge many-to-one protocol. As shown in FIG. 3, the burst of packets 20 are represented by a first packet 28, a second packet 30, and a third packet 32. Further, the processing of the first packet 28 is represented by a first packet pulse 34 while the processing of the second packet 30 is represented by a second packet pulse 36.
As further shown in FIG. 3, the host device completes the processing of the second packet 30 and during the trailing delay time T2, while the host device is transmitting an acknowledgement signal to the network interface device, the network interface device detects the third packet 32. The presence of the third packet 32 goes undetected because the interrupt signal V.sub.II is still asserted during the trailing delay time T2. Thus, since the third packet 32 has gone undetected, the third packet will remain stored in the network interface device until the next packet is detected and the interrupt signal V.sub.II is reasserted.
One solution to the problem of delayed notification is to recheck the network interface device each time the host device completes processing all of the packets detected by the network interface device. FIG. 4 shows a timing diagram which illustrates the host device rechecking a network interface device. As shown in FIG. 4, the burst of packets 20 includes a fourth packet 38 while the processing of the fourth packet is represented by a packet processing pulse 40. In addition, the series of packet processing pulses includes a rechecking pulse 42.
As shown in FIG. 4, when the fourth packet 38 has been processed and the interrupt signal V.sub.II has been acknowledged, the host device rechecks the network interface device, as shown by the rechecking pulse 42, to insure that no packet goes undetected.
The problem with rechecking the network interface each time the host device completes its processing is that the added step increases the management overhead required. Although the extra overhead depicted by rechecking pulse 42 appears to be a modest tradeoff to insure that packets are not delayed, when a rechecking pulse regularly accompanies the processing of a single packet, the extra overhead quickly becomes significant.
FIG. 5 shows a timing diagram which illustrates the host device rechecking the network interface device, as represented by the rechecking pulse 42, after a single packet 44 has been processed, as represented by a processing pulse 46. As shown in FIG. 5, when the host device is able to process each packet detected by the network interface device before a subsequent packet is detected, the additional overhead is present with each packet processed.
In addition to a process-then-acknowledge many-to-one protocol, which acknowledges the interrupt signal after all of the detected packets have been processed, an acknowledge-then-process many-to-one protocol, which acknowledges the interrupt signal before any packets are processed, can also be utilized. Under an acknowledge-then-process many-to-one protocol, as with the process-then-acknowledge many-to-one protocol, the network interface device detects a packet and then generates the interrupt signal in response.
Upon receiving the interrupt signal, the host device typically acknowledges the interrupt signal, thereby causing the interrupt signal to be deasserted, and then processes all of the packets detected by the network interface device. FIG. 6 shows a timing diagram which illustrates the operation of the host device and the peripheral device under an acknowledge-then-process many-to-one protocol.
The detection of a series of packets is represented in FIG. 6 as a series of packet pulses 52 where the falling edge 54 represents the detection of a complete packet. As with the process-then-acknowledge many-to-one protocol, the network interface device generates the rising edge 56 of the interrupt signal V.sub.II in response to the falling edge 54 of a completely detected packet.
The processing of each packet 52 by the host device is represented in FIG. 6 by a series of packet processing pulses 58. As shown in FIG. 6, the host device acknowledges the interrupt signal V.sub.II and then processes a detected packet.
The principal disadvantage of the acknowledge-then-process many-to-one protocol is the occurrence of a spurious interrupt condition. A spurious interrupt condition occurs when the network interface device generates an interrupt signal after the host device has acknowledged the interrupt signal but before the host device completes the processing of all of the detected packets. The spurious interrupt causes the host device to attempt to process packets which do not exist.
FIG. 7 shows a timing diagram which illustrates the generation of a spurious interrupt signal. As shown in FIG. 7, the burst of packets 52 are represented by a first packet 62, a second packet 64, and a third packet 66. Further, the processing of the packets are correspondingly represented by a first packet processing pulse 70, a second packet processing pulse 72, and a third packet processing pulse 74. In addition, the spurious interrupt signal is represented by a spurious packet processing pulse 76.
As further shown in FIG. 7, the network interface device generates the rising edge 56 of the interrupt signal V.sub.II in response to the falling edge 54 of the first detected packet 62. The host device acknowledges the interrupt signal V.sub.II and then begins processing the first packet 62. Before the host device completes the processing of the first packet 62, as shown by the packet processing pulse 70, the network interface device detects the second and the third packets 64 and 66, and reasserts the interrupt signal V.sub.II.
The host device processes all three of the packets 62, 64, and 66 detected by the network interface device. Since the interrupt signal V.sub.II was reasserted when the second packet 64 was detected, the host device reacknowledges the interrupt signal, as shown by the spurious packet processing pulse 76, and then attempts to process packets which do not exist.
One alternative to the acknowledge-then-process many-to-one protocol as described above is to acknowledge the interrupt signal before processing each packet. FIG. 8 shows a timing diagram which illustrates the effect of acknowledging the interrupt signal prior to processing each packet. As shown in FIG. 8, when an acknowledgement signal V.sub.AA is generated with the processing of each packet, three acknowledgements are generated when only one is required.
Thus, there is a need for an interrupt-acknowledgement circuit that generates a single interrupt signal when a plurality of events are detected and that allows a host device to process all of the detected events without delayed processing, the generation of spurious signals, or the use of additional overhead such as redundant checks or acknowledgements.